Design Summary: "pe_5_2"
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Reviewer Name/ID:
Metrics for pe_5_2 Tasks
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
102 |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
237.656MB |
02.390s |
02.837s |
02.837s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| --- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
3.696GB |
03.129s |
03.402s |
06.239s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
3 |
--- |
--- |
--- |
46.117um^2 |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
440 |
--- |
--- |
--- |
121 |
602 |
--- |
--- |
141.984MB |
03.009s |
06.987s |
13.227s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
40 |
--- |
--- |
64 |
47.370um^2 |
112.587um^2 |
42.075% |
0 |
0.000mw |
0.000mw |
--- |
--- |
--- |
0 |
504 |
0 |
31 |
108 |
121 |
590 |
--- |
--- |
455.020MB |
04.740s |
05.783s |
19.010s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
41 |
0 |
--- |
64 |
51.584um^2 |
112.587um^2 |
45.817% |
0 |
0.000mw |
0.000mw |
--- |
0 |
0 |
0 |
511 |
0 |
31 |
108 |
121 |
597 |
--- |
--- |
1.938GB |
07.940s |
09.212s |
28.223s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
39 |
0 |
--- |
64 |
51.584um^2 |
112.587um^2 |
45.817% |
0 |
0.000mw |
0.000mw |
--- |
0 |
0 |
0 |
511 |
0 |
31 |
108 |
121 |
597 |
--- |
--- |
526.578MB |
05.330s |
06.171s |
34.395s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
0 |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
--- |
538.516MB |
03.370s |
05.066s |
55.239s |
| errors |
warnings |
drvs |
drcs |
unconstrained |
cellarea |
totalarea |
utilization |
logicdepth |
peakpower |
leakagepower |
irdrop |
holdpaths |
setuppaths |
macros |
cells |
registers |
buffers |
inverters |
pins |
nets |
vias |
wirelength |
memory |
exetime |
tasktime |
totaltime |
| 0 |
39 |
0 |
--- |
64 |
51.584um^2 |
112.587um^2 |
45.817% |
0 |
0.000mw |
0.000mw |
0.003mv |
0 |
0 |
0 |
511 |
0 |
31 |
108 |
121 |
597 |
--- |
--- |
549.867MB |
19.379s |
20.137s |
01:10.310s |